1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit capable of output buffer or voltage hold, which can be suitably used in analog signal processing or multilevel signal processing.
2. Related Background Art
Source followers using NMOS transistors and constant-current power supplys have widely been used as an output buffer for analog signal processing and multilevel signal processing, designed using the MOS processes (or the CMOS processes).
FIG. 1 illustrates an example of the NMOS source follower. In a configuration with an NMOS transistor 50 for output drive whose gate terminal is an input terminal 3, whose source terminal is an output terminal 4, and whose drain terminal is connected to a power-supply voltage 5, a drain terminal of an NMOS transistor 51 for constant-current power supply is connected to the output terminal 4, the source terminal of the NMOS transistor 51 is connected to ground potential 6, and the gate terminal thereof is connected to a gate-drain common connection point of an NMOS transistor 52 whose source terminal is connected to the ground potential 6. A constant-current power supply 53 is connected between the gate-drain common connection point of NMOS transistor 52 and the power-supply voltage 5, and a current mirror circuit is constructed of the NMOS transistor 51 for constant-current power supply, the NMOS transistor 52, and the constant-current power supply 53.
When the NMOS transistor 51 for constant-current power supply and the NMOS transistor 52 have an equal ratio of W/L (W: channel width, L: channel length), the drain current the transistor 51 for constant-current power supply becomes equal to the current of the constant-current power supply 53. The drain current of the transistor 51 for constant-current power supply becomes a dc operating point or idling current of the NMOS transistor 50 for output drive. During driving of a load, in the case of a sink current load, the drain terminal of the transistor 51 for constant-current power supply draws the load driving current; in the case of a source current load, the load driving current is delivered from the drain terminal of the NMOS transistor 50 for output through the source terminal. Since the input terminal 3 is the gate terminal in this configuration, a signal from a preceding stage is received at high impedance; and the output terminal 4 is the source terminal, so that a load circuit of a subsequent stage can be driven at low impedance. In order to eliminate the substrate bias effect of MOS transistor so as to achieve linear input/output characteristics, the substrate terminal and source terminal of the NMOS transistor 50 for output drive are electrically connected.
When accurate transmission of dc voltage was tried to be carried out in analog processing and multilevel processing in the NMOS source follower circuit, a dc level shift equivalent to the gate-source voltage Vgs of the MOS transistor occurred to hinder the dc transmission, however. This phenomenon will be described using FIG. 2. FIG. 2 illustrates Id-Vgs characteristics of the NMOS transistor 50. When a voltage not less than the threshold voltage Vth is applied as the gate-source voltage Vgs, the drain current Id flows. Namely, when the drain current Id is allowed to flow, the gate-source voltage Vgs, which is determined by Vth and Id, appears. The source potential of the transistor 50 for output biased by Id, always becomes Vgs=V.alpha. smaller than the gate potential. This is the dc level shift between input and output. This shift is not constant and varies within a certain range. Namely, the shift has a variation distribution because of the principal factors including manufacturing variations of Vth of NMOS transistor 50 for output and setting variations of the drain current of the transistor 51 for constant-current power supply. As described, the dc level shift due to Vgs is not constant and in addition, Vgs also has a temperature drift. It is thus not easy to achieve accurate transmission of signals including dc values by the circuit shown in FIG. 1. Some Vgs-canceling circuits were also proposed, but they increased the number of circuit components and also increased electric power consumption, thus being a hindrance against increase in integration.
Considering applications to the analog processing, this problem of output dc level shift makes accurate dc-linked signal processing difficult. Considering applications to voltage mode multiple-valued logic circuits, the occurrence of dc level shift in the buffer will considerably degrade the noise margin of multilevel signal processing.
FIG. 3 is a circuit setup diagram to show an example of a complementary source follower. The gate terminals of respective NMOS transistor 340 and PMOS transistor 341 are connected to each other to compose an input terminal 305, the source terminals of the respective transistors are connected to each other to compose an output terminal 306, the drain terminal of the NMOS transistor 340 is connected to power-supply voltage 307, the drain terminal of the PMOS transistor 341 is connected to ground potential 308, and the load driving current is delivered from the drain terminal through the source terminal. Since the input terminal 305 is composed of the gate terminals of the both transistors in this configuration, the signal from the preceding stage is received at high impedance; since the output terminal 306 is composed of the source terminals of the both transistors, the load circuit of the subsequent stage can be driven at low impedance. In order to eliminate the substrate bias effect of the MOS transistors to achieve linear input/output characteristics, the substrate terminal and source terminal of each of the NMOS transistor 340 and PMOS transistor 341 are electrically connected.
FIG. 4 is a circuit setup diagram of another complementary source follower. The gate terminals of respective NMOS transistor 350 and PMOS transistor 351 are connected to each other, the drain terminal of the NMOS transistor 350 is connected to power-supply voltage 307, and the source terminal thereof is connected to constant-current power supply 354 and also to the gate terminal of PMOS transistor 353 for output drive. The drain terminal of the PMOS transistor 351 is connected to ground potential 308, and the source terminal thereof is connected to constant-current power supply 355 and also to the gate terminal of NMOS transistor 352 for output drive. The source terminals of the respective NMOS transistor 352 and PMOS transistor 353 are connected to each other to compose the output terminal 306 to drive a capacitive load at high speed. The drain terminal of the NMOS transistor 352 is connected to the power-supply voltage 307, the drain terminal of the PMOS transistor 353 is connected to the ground potential 308, and thus the load driving current is delivered from the drain terminal through the source terminal. Since the input terminal 305 is the connection point between the gate terminals of the two transistors in this configuration, the signal from the preceding stage is received at high impedance; since the output terminal 306 is composed of the source terminals of the two MOS transistors, the load circuit of the subsequent stage can be driven at low impedance. In the case where the ratios W/L (W: channel width, L: channel length) of the pair of PMOS transistors 351, 353 and the pair of NMOS transistors 350, 352 are equal to each other, where the currents of the constant-current power supplys 354 and 355 are Iss1 and Iss2, respectively, and where Iss=Iss1=Iss2, the idling current Ibias, which penetrates the NMOS transistor 352 and PMOS transistor 353 composing the output drive stage, is Iss, so that the gate-source voltages of the respective pairs of PMOS transistors 351, 353 and NMOS transistors 350, 352 are equal to each other. Therefore, no dc level shift occurs between the input terminal 305 and the output terminal 306. In order to eliminate the source bias effect of the MOS transistors to achieve the linear input/output characteristics, the substrate terminal and source terminal of each of the NMOS transistors 350, 352 and PMOS transistors 351, 353 are electrically connected.
Features of the complementary source follower are as follows. When the current flows from the output terminal to the load, the NMOS transistor 352 delivers the load driving source current; when the current flows from the load to the output terminal, the PMOS transistor 353 delivers the load driving sink current; whereby high-speed driving is allowed against a load of a large capacity.
When accurate transmission of dc voltage was tried to be carried out in analog processing and multilevel processing in the complementary source follower circuit, there arose, however, a problem of occurrence of output offset voltage due to a relative difference of threshold voltage Vth between the NMOS and PMOS transistors. This problem will be described using the complementary source follower circuit of FIG. 3. The dc operating point of this circuit is determined as an idling current in a state where the drain currents of the NMOS transistor 340 and PMOS transistor 341 are equal. When the threshold voltages Vth of the respective NMOS transistor 340 and PMOS transistor 341 are equal to each other, a very small drain current flows to bias the gate-source voltage Vgs of each MOS transistor to 0 V, thus generating no output offset voltage. When the relative difference of Vth occurs between NMOS and PMOS, the drain currents as idling currents of the NMOS transistor 340 and PMOS transistor 341 are equal to each other, and thus the voltages Vgs are different between the two transistors because of the difference of Vth. For example, when Vth of the NMOS transistor 340 is greater, Vgs of the NMOS transistor 340 during idling also becomes larger, so as to produce a negative offset in the output. When Vth of the PMOS transistor 341 is greater, Vgs of the PMOS transistor 341 during idling becomes larger, so as to produce a positive offset in the output. There is no relative matching element for the Vth characteristics between NMOS and PMOS in terms of fabrication in the CMOS processes, and thus the output offset varies depending upon manufacturing variation of Vth.
The complementary source follower circuit of FIG. 4 is a circuit for ideally canceling the relative difference of Vth between NMOS and PMOS and thus generating no output offset. When W/L between the NMOS transistors 350, 352 and W/L between the PMOS transistors 351, 353 are equal, the idling current Ibias flowing between the NMOS transistor 352 and the PMOS transistor 353 composing the output drive stage becomes equal to Iss (=Iss1=Iss2), so that Vgs between the NMOS transistors 350, 352 and Vgs between the PMOS transistors 351, 353 also become equal to each other. At this time the following equation holds. EQU Vgs350(Iss1)+Vgs353(Ibias)=Vgs351(Iss2)+Vgs352(Ibias)
As long as the above equation is satisfied, no offset voltage appears at the output terminal 306 even with a relative difference of Vth between NMOS and PMOS. There are, however, cases where the relation of Iss1=Iss2 is not achieved because of mismatch between the current mirrors of the constant-current power supply 354 for supplying Iss1 and the constant-current power supply 355 for supplying Iss2 whereby an offset voltage thus appears at the output. Further, the complementary source follower circuit of FIG. 4 needs to include the NMOS source follower composed of the NMOS transistor 350 and the constant-current power supply 354, the PMOS source follower composed of the PMOS transistor 351 and the constant-current power supply 355, and the bias circuits for setting of Iss1, Iss2, in addition to the output drive MOS transistors, so that the circuit scale becomes so large. This circuit necessitates the currents Iss1, Iss2 and the currents of the bias circuits in addition to the idling current of output, thus increasing the electric power consumption. The increase of circuit scale increases a chip layout area and thus increases the electric power consumption, and it in turn results in creating temperature gradient in the chip to degrade Vgs matching characteristics of the MOS transistors. This was a cause of the temperature drift of output offset. In some cases, occurrence of this output offset could make the accurate dc-coupled signal processing difficult in the case of applications to the analog processing. Considering applications to the voltage mode multiple-valued logic circuits, the occurrence of offset in the buffer could considerably degrade the noise margin of multilevel signal processing in some cases.